KS0127B Data Sheet
PIN DESCRIPTION
Pin Name
INPUT
AY0
AY1
AY2
AC0
AC1
AC2
XTALI
XTALO
RST
84
86
88
90
92
94
8
7
10
I
I
I
I
I
I
I
O
I
Pin #
Type
Description
MULTIMEDIA VIDEO
1 of 6 analog CVBS or 1of 3 S-video Y inputs.
1 of 6 analog CVBS or 1of 3 S-video Y inputs.
1 of 6 analog CVBS input or 1 of 3 S-video Y inputs or Y input for 3
wire component input
1 of 6 analog CVBS or 1 of 3 S-video C inputs.
1 of 6 analog CVBS or 1 of 3 S-video C inputs or Cb input for 3 wire
component input
1 of 6 analog CVBS or 1 of 3 S-video C inputs or Cr input for 3 wire
component input
Pin 1 for an external crystal or TTL clock input.
Pin 2 for an external crystal.
Chip reset. Active low signal.
OUTPUT (All output pins can be selectively three-stated)
Y0 - Y7, C0 - C7 45-48,53-56,33-
39,44
EXV0 - EXV7
16,27,28,61-63,
68,71
O
I/O
Digital video outputs.
Expanded digital video I/O port. Can be configured as an additional
8-bit output port (no scaling), or additional outputs of the main digital
output stream for 24 bit output modes, as an 8-bit input for direct
digital access of the down scaler.
Programmable horizontal timing signal. One pulse every video line.
When the EXV port is configured as an input, this pin can be
programmed as an input.
Programmable horizontal timing signal. One pulse every video line.
At power up, this pin needs a 10 kΩ pull-down resistor to configure
the chip to operate in IIC mode.
Programmable vertical timing signal. When the EXV port is
configured as an input, this pin can be programmed as an input.
Programmable horizontal active video flag.
Programmable vertical active video flag.
During reset, the pin is an input and the logic state of this pin is
latched into the
OENC[0]
register bit. Use a 10 kΩ resistor for pull-up
or pull-down.
Valid pixel data flag. Polarity is programmable. Active when output
video data is valid.
HS1
26
I/O
HS2(IIC)
76
I/O
VS
HAV
VAV(OENC0)
23
25
3
I/O
O
I/O
EHAV
5
O
Modified on May/04/2000
ELECTRONICS
PAGE 4 OF 96
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