CMOS 512 × 9 FIFO
LH5496/96H
are shared by all devices, while internal logic controls the
steering of data. Only one FIFO will be enabled for any
given read cycle, so the common Data Out pins of all
devices are wire-ORed together. Likewise, the common
Data In pins of all devices are tied together.
OPERATIONAL MODES (cont’d)
Depth Expansion
Depth expansion is implemented by configuring the
required number of FIFOs in Expansion mode. In this
arrangement, the FIFOs are connected in a circular fash-
ion with the Expansion Out pin (XO) of each device tied
totheExpansion In pin (XI) of the nextdevice. One FIFO
in this group must be designated as the first load device.
This is accomplished by tying the First Load pin (FL) of
this device to ground. All other devices must have their
FL pin tied to a high level. In this mode, W and R signals
In Expansion mode, external logic is required to gen-
erate a composite Full or Empty flag. This is achieved by
ORing the FF pins of all devices and ORing the EF pins
of all devices respectively. The Half-Full flag and
Retransmit functions are not available in Depth Expan-
sion mode.
XO
R
W
9
9
9
DATA IN
D0 - D8
9
DATA OUT
Q0 - Q8
LH5496/96H
EF
FL
FF
RS
Vcc
XI
XO
9
9
LH5496/96H
FF
EF
FL
FULL
EMPTY
Vcc
RS
XI
XO
9
9
FF
EF
FL
LH5496/96H
RS
RS
XI
5496-19
Figure 19. FIFO Depth Expansion (1536 × 9)
13
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