C8051F310/1/2/3/4/5/6/7
8.2.
Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The CIP-51 memory organization is
shown in Figure 8.2.
PROGRAM/DATA MEMORY
(Flash)
C8051F310/1
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
0xFF
0x80
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
(Direct Addressing Only)
0x3E00
0x3DFF
RESERVED
(Direct and Indirect
Addressing)
16 kB Flash
(In-System
Programmable in 512
Byte Sectors)
0x30
0x2F
0x20
0x1F
Bit Addressable
Lower 128 RAM
(Direct and Indirect
Addressing)
0x00
General Purpose
Registers
EXTERNAL DATA ADDRESS SPACE
0x0000
0xFFFF
C8051F312/3/4/5
0x2000
0x1FFF
RESERVED
Same 1024 bytes as from
0x0000 to 0x03FF, wrapped
on 1 kB boundaries
8 kB Flash
(In-System
Programmable in 512
Byte Sectors)
0x0400
0x03FF
0x0000
XRAM - 1024 Bytes
(accessable using MOVX
instruction)
0x0000
Figure 8.2. Memory Map
8.2.1. Program Memory
The CIP-51 core has a 64k-byte program memory space. The C8051F310/1 and C8051F312/3/4/5 imple-
ment 16 and 8 kB, respectively, of this program memory space as in-system, re-programmable Flash
memory, organized in a contiguous block from addresses 0x0000 to 0x3FFF or 0x0000 to 0x1FFF.
Addresses above 0x3E00 are reserved on the 16 kB devices.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro-
vides a mechanism for the CIP-51 to update program code and use the program memory space for non-
volatile data storage. Refer to
for further details.
Rev. 1.7
85
SILABS [ SILICON LABORATORIES ]
