C8051F80x-83x
Port
P0
4
P1
41 51 61 71
0
Pin Number
0
1
2
3
5
6
7
0
1
2
3
Special
Function
Signals
TX0
RX0
SCK
MISO
MOSI
NSS2
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Pin Skip
Settings
P0SKIP
P1SKIP
In this example, the crossbar is configured to assign the UART TX0 and
RX0 signals, the SPI signals, and the PCA signals. Note that the SPI
signals are assigned as multiple signals. Additionally, pins P0.0, P0.2, and
P0.3 are configured to be skipped using the P0SKIP register.
These boxes represent the port pins which are used by the peripherals
in this configuration.
1st TX0 is assigned to P0.4
2
3
nd RX0 is assigned to P0.5
rd SCK, MISO, MOSI, and NSS are assigned to P0.1, P0.6, P0.7, and
P1.0, respectively.
4th CEX0, CEX1, and CEX2 are assigned to P1.1, P1.2, and P1.3,
respectively.
All unassigned pins, including those skipped by XBR0 can be used as
GPIO or for other non-crossbar functions.
Notes:
1. P1.4-P1.7 are not available on 16-pin packages.
2. NSS is only pinned out when the SPI is in 4-wire mode.
Figure 23.6. Priority Crossbar Decoder Example 2—Skipping Pins
146
Rev. 1.0
SILICON [ SILICON ]
