Si1010/1/2/3/4/5
5.3. 8-Bit Mode
Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode.In 8-bit mode, only the
8 MSBs of data are converted, allowing the conversion to be completed in two fewer SAR clock cycles
than a 10-bit conversion. This can result in an overall lower power consumption since the system can
spend more time in a low power mode. The two LSBs of a conversion are always 00 in this mode, and the
ADC0L register will always read back 0x00.
5.4. 12-Bit Mode
Si1010/1/2/3/4/5 devices have an enhanced SAR converter that provides 12-bit resolution while retaining
the 10- and 8-bit operating modes of the other devices in the family. When configured for 12-bit conver-
sions, the ADC performs four 10-bit conversions using four different reference voltages and combines the
results into a single 12-bit value. Unlike simple averaging techniques, this method provides true 12-bit res-
olution of ac or dc input signals without depending on noise to provide dithering. The converter also
employs a hardware Dynamic Element Matching algorithm that reconfigures the largest elements of the
internal DAC for each of the four 10-bit conversions to cancel the any matching errors, enabling the con-
verter to achieve 12-bit linearity performance to go along with its 12-bit resolution. For best performance,
the Low Power Oscillator should be selected as the system clock source while taking 12-bit ADC measure-
ments.
The 12-bit mode is enabled by setting the AD012BE bit (ADC0AC.7) to logic 1 and configuring Burst Mode
for four conversions as described in Section 5.2.3. The conversion can be initiated using any of the meth-
ods described in Section 5.2.1, and the 12-bit result will appear in the ADC0H and ADC0L registers. Since
the 12-bit result is formed from a combination of four 10-bit results, the maximum output value is 4 x (1023)
= 4092, rather than the max value of (2^12 – 1) = 4095 that is produced by a traditional 12-bit converter. To
further increase resolution, the burst mode repeat value may be configured to any multiple of four conver-
sions. For example, if a repeat value of 16 is selected, the ADC0 output will be a 14-bit number (sum of
four 12-bit numbers) with 13 effective bits of resolution.
5.5. Low Power Mode
The SAR converter provides a low power mode that allows a significant reduction in operating current
when operating at low SAR clock frequencies. Low power mode is enabled by setting the AD0LPM bit
(ADC0PWR.7) to 1. In general, low power mode is recommended when operating with SAR conversion
clock frequency at 4 MHz or less. See the Electrical Characteristics chapter for details on power consump-
tion and the maximum clock frequencies allowed in each mode. Setting the Low Power Mode bit reduces
the bias currents in both the SAR converter and in the High-Speed Voltage Reference. Table 5.1describes
the various modes of the ADC.
Rev. 1.0
83
SILABS [ SILICON LABORATORIES ]
