Si1010/1/2/3/4/5
Table 5.1. Representative Conversion Times and Energy Consumption for the SAR ADC
with 1.65V High-Speed VREF
Normal Power Mode
Low Power Mode
8 bit
10 bit
12 bit
8 bit
10 bit
12 bit
8.17
MHz
4.08
MHz
4.08
MHz
Highest nominal SAR
clock frequency
Total number of
conversion clocks
required
8.17MHz
6.67 MHz
(20.0 / 3)
4.00 MHz
(20.0 / 5)
(24.5 / 3) (24.5 / 3)
(24.5 / 6) (24.5 / 6)
52
(13*4)
52
(13*4)
11
13
11
13
4.8 us
4.8 us
Total tracking time (min)
Total time for one
conversion
1.5 us
1.5 us
(1.5+3*1.1)
1.5 us
1.5 us
(1.5+3*1.1)
2.85 us
3.09 us
12.6 us
79 ksps
36.5 nJ
4.19 us
4.68 us
17.8 us
56 ksps
27.7 nJ
ADC Throughput
351 ksps 323 ksps
238 ksps 214 ksps
Energy per conversion
8.2 nJ 8.9 nJ
6.5 nJ 7.3 nJ
Note: This table assumes that the 24.5 MHz precision oscillator is used for 8- and 10-bit modes, and the 20 MHz low
power oscillator is used for 12-bit mode. The values in the table assume that the oscillators run at their nominal
frequencies. The maximum SAR clock values given in Table 4.10 allow for maximum oscillation frequencies of
25.0 MHz and 22 MHz for the precision and low-power oscillators, respectively, when using the given SAR
clock divider values. Energy calculations are for the ADC subsystem only and do not include CPU current.
84
Rev. 1.0
SILICON [ SILICON ]
