Si3056
Si3018/19/10
Table 9. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = 1)
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
1, 2
Symbol
Min
Typ
Max
Unit
Parameter
Cycle Time, SCLK
t
244
—
1/256 Fs
—
—
20
20
20
20
20
—
—
ns
%
c
SCLK Duty Cycle
t
50
—
—
—
—
—
—
—
dty
Delay Time, SCLK↑ to FSYNC↑
Delay Time, SCLK↑ to FSYNC↓
Delay Time, SCLK↑ to SDO Valid
Delay Time, SCLK↑ to SDO Hi-Z
Delay Time, SCLK↑ to FSD↓
Setup Time, SDO Before SCLK↓
Hold Time, SDO After SCLK↓
Notes:
t
—
ns
ns
ns
ns
ns
ns
ns
d1
d2
d3
d4
d5
t
—
t
t
t
—
—
—
t
25
20
su
t
h
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V.
2. See "5.27.Multiple Device Support" on page 38 for functional details.
tc
SCLK
td1
td2
FSYNC
(mode 1)
td3
tsu
th
td4
SDO
D15
D14
D13
D0
(master)
td3
SDO
D15
td5
(slave 1)
FSD
SDI
tsu
th
D14
D15
D1
D0
Figure 5. Serial Interface Timing Diagram (DCE = 1, FSD = 1)
Rev. 1.05
13
SILICON [ SILICON ]
