Si3056
Si3018/19/10
Table 7. Switching Characteristics—Serial Interface (Master Mode, DCE = 0)
(V
D
= 3.0 to 3.6 V, T
A
=
0 to 70 °C, C
L
= 20 pF)
Parameter
Cycle time, SCLK
SCLK Duty Cycle
Delay Time, SCLK↑ to FSYNC↓
Delay Time, SCLK↑ to SDO Valid
Delay Time, SCLK↑ to FSYNC↑
Setup Time, SDI Before SCLK
↓
Hold Time, SDI After SCLK
↓
Setup Time, FC↑ Before SCLK↑
Hold time, FC↑ After SCLK↑
Symbol
t
c
t
dty
t
d1
t
d2
t
d3
t
su
t
h
t
sfc
t
hfc
Min
244
—
—
—
—
25
20
40
40
Typ
1/256 Fs
50
—
—
—
—
—
—
—
Max
—
—
20
20
20
—
—
—
—
Unit
ns
%
ns
ns
ns
ns
ns
ns
ns
Note:
All timing is referenced to the 50% level of the waveform. Input test levels are V
IH
= V
D
– 0.4 V, V
IL
= 0.4 V.
SCLK
t
c
V
OH
V
OL
t
d1
t
d3
FSYNC
(mode 0)
FSYNC
(mode 1)
16-Bit
SDO
t
d3
t
d2
D15
t
su
D14
t
h
D1
D0
D0
16-Bit
SDI
D15
D14
D1
t
sfc
D0
t
hfc
FC
Figure 3. Serial Interface Timing Diagram (DCE = 0)
Rev. 1.05
11
SILABS [ SILICON LABORATORIES ]
