Si5338
3.7.2. Enabling Outputs through the I
2
C Interface
Output enable can be controlled through the I
2
C
interface. As shown in Figure 13, register 230[3:0]
allows control of each individual output driver. Register
230[4] controls all drivers at once. When register 230[4]
is set to disable all outputs, the individual output
enables will have no effect. Registers 110[7:6], 114[7:6],
118[7:6], and 112[7:6] control the output disabled state
as tri-state, low, high, or always on. If always on is set,
that output will always be on regardless of any other
register or chip state. In addition, the always on mode
must be selected for an output that is fed back in a Zero
Delay application.
7
6
5
4
3
2
1
0
3.8. Reset Options
There are two types of resets on the Si5338, POR and
soft reset. A POR reset automatically occurs whenever
the supply voltage on the VDD is applied.
The soft reset is forced by writing 0x02 to register 246.
This bit is not self-clearing, and thus it may read back as
a 1 or a 0. A soft reset will not download any pre-
programmed NVM and will not change any register
values in RAM.
The soft reset performs the following sequence:
1. All outputs turn off except if programmed to be
always on.
2. Internal calibrations are done and MultiSynths are
initialized.
a. Outputs that are synchronous are phase
aligned (if Rn = 1).
3. 25 ms is allowed for the PLL to lock (no delay occurs
when FCAL_OVRD_EN = 1).
4. Turn on all outputs that were turned off in step 1.
230
OEB OEB OEB OEB OEB
All
3
2
1
0
0 = enable
1 = disable
Bits reserved
3.9. Features of the Si5338
7
6
5
4
3
2
1
0
110
CLK0 OEB
State
7
6
5
4
3
2
1
0
114
CLK1 OEB
State
The Si5338 offers several features and functions that
are useful in many timing applications. The following
paragraphs describe in detail the main features and
typical applications. All of these features can be easily
configured using the ClockBuilder Desktop. See "3.1.1.
3.9.1. Frequency Increment/Decrement
Each of the output clock frequencies can be
independently stepped up or down in predefined steps
as low as 1 ppm per step and with a resolution of
1 ppm. Setting of the step size and control of the
frequency increment or decrement is accomplished
through the I
2
C interface. Alternatively, the Si5338 can
be ordered with optional frequency increment (FINC)
and frequency decrement (FDEC) pins for pin-
controlled applications. See Table 18 for ordering
information of pin-controlled devices.
The frequency increment and decrement feature is
useful in applications requiring a variable clock
frequency (e.g., CPU speed control, FIFO overflow
management, etc.) or in applications where frequency
margining (e.g., f
out
±5%) is necessary for design
verification and manufacturing test. Frequency
increment or decrement can be applied as fast as
1.5 MHz when it is done by pin control. When under I
2
C
control, the frequency increment and decrement update
rate is limited by the I
2
C bus speed. The magnitude of
the frequency step has 0 ppm error. Frequency steps
are seamless and glitchless.
7
6
5
4
3
2
1
0
118
CLK2 OEB
State
7
6
5
4
3
2
1
0
122
CLK3 OEB
State
00 = disabled tri-state
01 = disabled low
10 = disabled high
11 = always enabled
Bits used by other functions
Figure 13. Output Enable Control Registers
Rev. 0.6
23
SILABS [ SILICON LABORATORIES ]
