Si5338
3.9.2. Output Phase Increment/Decrement
Non-unity settings of R0 will affect the Finc/Fdec step
size at the MultiSynth0 output. For example, if the
MultiSynth0 output step size is 2.56 MHz and R0 = 8,
the step size at the output of R0 will be 2.56 MHz
divided by 8 = .32 MHz. When the Rn divider is set to
non-unity, the initial phase of the CLKn output with
respect to other CLKn outputs is not guaranteed.
The Si5338 has a digitally-controlled glitchless phase
increment and decrement feature that allows adjusting
the phase of each output clock in relation to the other
output clocks. The phase of each output clock can be
adjusted with an accuracy of 20 ps over a range of
±45 ns. Setting of the step size and control of the phase
increment or decrement is accomplished through the 3.9.5. Zero-Delay Mode
2
I C interface. Alternatively, the Si5338 can be ordered
The Si5338 supports an optional zero delay mode of
with optional phase increment (PINC) and phase
decrement (PDEC) pins for pin-controlled applications.
In pin controlled applications the phase increment and
decrement update rate is as fast as 1.5 MHz. In I C
applications, the maximum update rate is limited by the
operation for applications that require minimal input-to-
output delay. In this mode, one of the device output
clocks is fed back to the feedback input pin (IN4 or IN5/
IN6) to implement an external feedback path essentially
nullifying the delay between the reference input and the
output clocks. Figure 14 shows the Si5338 in a typical
zero-delay configuration. It is generally recommended
2
2
speed of the I C. See Table 18 for ordering information
of pin-controlled devices.
The phase increment and decrement feature provides a that Clk3 be LVDS and that the feedback input be pins 5
useful method for fine tuning setup and hold timing and 6. For the differential input configuration to pins 5
margins or adjusting for mismatched PCB trace lengths. and 6, see Figure 3 on page 17. The zero-delay mode
combined with the phase increment/decrement feature
allows unprecedented flexibility in generating clocks
with precise edge alignment.
3.9.3. Initial Phase Offset
Each output clock can be set for its initial phase offset
up to ±45 ns. In order for the initial phase offset to be
applied correctly at power up, the VDDOx output supply
voltage must cross 1.2 V before the VDD (pins 7,24)
Si5338
core power supply voltage crosses 1.45 V. This applies
M0
M1
M2
M3
R0
R1
R2
R3
Clk0
Clk1
Clk2
to the each driver output individually. A soft_reset will
also guarantee that the programmed Initial Phase Offset
is applied correctly. The initial phase offset only works
on outputs that have their R divider set to 1.
Clk
Input
P1
P2
PLL
3.9.4. Output R Divider
When the requested output frequency of a channel is
below 5 MHz, the Rn (n = 0,1,2,3) divider needs to be
set and enabled. This is automatically done in register
maps generated by the ClockBuilder Desktop. When
the Rn divider is active the step size range of the
frequency increment and decrement function will
decrease by the Rn divide ratio. The Rn divider can be
set to {1, 2, 4, 8, 16, 32}.
Clk3
Figure 14. Si5338 in Zero Delay Clock
Generator Mode
24
Rev. 0.6
SILICON [ SILICON ]
