Si85xx
1. Electrical Specifications
Table 1. Electrical Specifications
TA = –40 to +85 ºC (typical specified at 25 ºC), VDD = 2.7 to 5.5 V
Parameter
Supply Voltage (V
DD
)
Supply Current
Undervoltage Lockout (V
UVLO
)
Undervoltage Lockout Hysteresis
(V
HYST
)
Logic Input HIGH Level
Logic Input LOW Level
Reset Time (t
R
)
R1, R2, R3, R4 Input Rise Time (t
RR
)
R1, R2, R3, R4 Input Fall Time (t
FR
)
Measurement Watchdog Timeout (t
WD
)
Series Input Resistance
Series Inductance
Input/Output Delay
Start-Up Self-Cal Delay (t
CAL
)
Input Common Mode Voltage Range
Operating Input Frequency Range (f)
DC Power Supply Rejection Ratio
Sensitivity
Conditions
Min
2.7
Typ
—
4
2.3
100
—
—
—
—
—
50
1.3
2
50
150
—
—
80
400
200
100
10
50
Max
5.5
7
2.5
—
—
0.8
—
30
30
80
—
—
100
200
1,000
1,200
—
—
—
—
—
—
30
Unit
V
mA
V
mV
V
V
ns
ns
ns
µs
mΩ
nH
ns
µs
V
kHz
db
mV/A
mV/A
mV/A
mV
V/µs
Ω
%
%
%
Fully enabled, input frequency =
1 MHz
—
2.1
—
MODE, R1, R2, R3, R4 inputs
(TTL compatible)
2.0
—
250
—
—
30
Measured from IIN to IOUT
Measured from IIN to IOUT
OUT, OUT1, OUT2 delay relative to
input
Time from VDD = V
UVLO
+ V
HYST
to
cal complete
—
—
—
—
—
50
—
Si85x1/4/7
Si85x2/5/8
Si85x3/6/9
—
—
—
—
—
20
OUT, OUT1, OUT2 Offset Voltage
(V
OUTMIN
)
VOUT Slew Rate
OUT, OUT1, OUT2 Output Resistance
Measurement Error (%)—all devices
(–40 to 85 ºC Temp Range)
Current flow from I
IN
to I
OUT
= 0
OUT, OUT1, OUT2 load = 5K || 50 pF
5 to 10% of full scale
10 to 20% of full scale
20 to 100% of full scale
–20
–10
–5
—
—
—
+20
+10
+5
4
Preliminary Rev. 0.1
SILABS [ SILICON LABORATORIES ]
