Si85xx
Integrator reset option 1 is selected by connecting T
RST
to VDD. In this mode, the Si85xx is held in reset as long
as the signals on R1-R4 satisfy the logic equations of
Tables 3 and 4. It is typically used in applications where
the gate drivers are external to the system controller I.C.
(the gate driver delay ensures reset is completed prior
to the start of measurement).
Reset option 2 is selected by connecting a timing
resistor (R
TRST
in Figure 4) from the TRST input to
ground. It is typically used in applications where the
gate drivers are on-board the controller. In this mode,
the on-chip reset timer is triggered when the signals on
R1-R4 satisfy the logic equations of Tables 3 and 4.
Once triggered, the timer maintains integrator in reset
for time duration t
R
as programmed by the value of
resistor R
TRST
. The user must select the value of
resistor R
TRST
to terminate the reset cycle prior to the
start of measurement under worst-case timing
conditions. Note that values of t
R
below the specified
value in Section “1. Electrical Specifications” results in
increased integrator output offset error and increased
output noise on VOUT. Moreover, t
R
’s time is
summarized by the following equation:
t
R
= 10 ns/kΩ
where values of R
TRST
that produce a reset time less
than 200 ns (R
TRST
< 20 kΩ) should not be used.
2.4. Effect of Operating Frequency on
Output Accuracy
The Si85xx includes a built-in watchdog timer that
disables measurement and holds OUT or OUT1 and
OUT2 at their minimum values when the timer’s preset
limit is exceeded. This timer limits the operation of the
Si85xx in dc measurement applications. As Figure 5
illustrates, the Si85xx operates down to about 10 kHz
with the nominal measurement error doubling to about
10 percent.
15%
% Typical Error
12%
9%
6%
3%
0%
10
20
30
Frequency (kHz)
40
50
Figure 5. Full-Scale Error vs. Frequency
2.5. Effect of Temperature on Accuracy
Offset voltage present at the Si85xx output terminals
(output offset voltage) is calibrated out each time VDD is
applied to the Si85xx; so, its error contribution is
minimized when the temperature at which calibration
occurred is at or near the steady-state operating
temperature of the Si85xx. For example, applying VDD
at 25 °C (offset cal is performed) and operating at 85 °C
will result in a larger offset error than operating at 50 ºC.
The effect of this error is summarized in Figure 6. The
chart is referenced to 25 °C. If the Si85xx is powered up
at 25 °C and then operated at 125 °C with no auto-
calibration performed (i.e., the power is not cycled at
125 °C, which causes an auto-calibration), a 3 percent
measurement error can be expected.
1.0%
0.5%
% Typical Error
0.0%
-0.5%
-1.0%
-1.5%
-2.0%
-2.5%
-3.0%
-3.5%
0
25
50
75
100
125
Temperature (Celcius)
Si85xx
TRST
R
TRST
Figure 4. Programming Reset Time (t
R
)
Figure 6. Differential Temperature
Calibration Error
8
Preliminary Rev. 0.1
SILABS [ SILICON LABORATORIES ]
