SiM3U1xx
Table 3.2. Power Consumption (Continued)
Parameter
Analog Peripheral Supply Currents
Voltage Regulator (VREG0)
I
VREGIN
Normal Mode, T
A
= 25 °C
BGDIS = 0, SUSEN = 0
Normal Mode, T
A
= 85 °C
BGDIS = 0, SUSEN = 0
Suspend Mode, T
A
= 25 °C
BGDIS = 0, SUSEN = 1
Suspend Mode, T
A
= 85 °C
BGDIS = 0, SUSEN = 1
Sleep Mode, T
A
= 25 °C
BGDIS = 1, SUSEN = X
Sleep Mode, T
A
= 85 °C
BGDIS = 1, SUSEN = X
External Regulator (EXTVREG0)
I
EXTVREG
Regulator
Current Sensor
PLL0 Oscillator (PLL0OSC)
USB0 Oscillator (USB0OSC)
Low-Power Oscillator (LPOSC0)
I
PLLOSC
I
USBOSC
I
LPOSC
Operating at 80 MHz
Operating at 48 MHz
Operating at 20 MHz
Operating at 2.5 MHz
Low-Frequency Oscillator
(LFOSC0)
I
LFOSC
Operating at 16.4 kHz,
T
A
= 25 °C
Operating at 16.4 kHz,
T
A
= 85 °C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
300
—
75
—
90
—
215
7
1.75
770
190
40
215
—
—
650
—
115
—
500
250
—
1.86
830
—
—
—
500
µA
µA
µA
µA
nA
nA
µA
µA
mA
µA
µA
µA
nA
nA
Symbol
Conditions
Min
Typ
Max
Units
Notes:
1.
Perhipheral currents drop to zero when peripheral clock and peripheral are disabled, unless otherwise noted.
2.
Currents are additive. For example, where
I
DD
is specified and the mode is not mutually exclusive, enabling the
functions increases supply current by the specified amount.
3.
I
ncludes all peripherals that cannot have clocks gated in the Clock Control module.
4.
Includes supply current from internal regulator and PLL0OSC (>48 MHz), USB0OSC (48 MHz) or LPOSC0 (<48 MHz).
5.
Flash execution numbers use 2 wait states for 80 MHz, 1 wait state for 48 MHz, and 0 wait states at 20 MHz or less.
6.
RAM execution numbers use 0 wait states for all frequencies.
7.
IDAC output current and IVC input current not included.
8.
Bias current only. Does not include dynamic current from oscillator running at speed.
12
Preliminary Rev. 0.8
SILABS [ SILICON LABORATORIES ]
