SiM3U1xx
Table 3.2. Power Consumption (Continued)
Parameter
Flash Current on VDD
Write Operation
Erase Operation
Notes:
Symbol
Conditions
Min
Typ
Max
Units
I
—
—
—
—
8
mA
mA
FLASH-W
I
15
FLASH-E
1. Perhipheral currents drop to zero when peripheral clock and peripheral are disabled, unless otherwise noted.
2. Currents are additive. For example, where I is specified and the mode is not mutually exclusive, enabling the
DD
functions increases supply current by the specified amount.
3. Includes all peripherals that cannot have clocks gated in the Clock Control module.
4. Includes supply current from internal regulator and PLL0OSC (>48 MHz), USB0OSC (48 MHz) or LPOSC0 (<48 MHz).
5. Flash execution numbers use 2 wait states for 80 MHz, 1 wait state for 48 MHz, and 0 wait states at 20 MHz or less.
6. RAM execution numbers use 0 wait states for all frequencies.
7. IDAC output current and IVC input current not included.
8. Bias current only. Does not include dynamic current from oscillator running at speed.
Table 3.3. Power Mode Wake Up Times
Parameter
Symbol
Conditions
Min
—
Typ
425
1.35
12
Max
—
Units
µs
Power Mode 3 Fast Wake Time
Power Mode 3 Wake Time
Power Mode 9 Wake Time
t
PM3FW
t
t
—
—
ms
PM3
PM9
—
—
µs
14
Preliminary Rev. 0.8
SILICON [ SILICON ]
