SiM3U1xx
Table 3.4. Reset and Supply Monitor
Parameter
V
DD
High Supply Monitor Threshold
(VDDHITHEN = 1)
V
DD
Low Supply Monitor Threshold
(VDDHITHEN = 0)
V
REGIN
Supply Monitor Threshold
Power-On Reset (POR) Threshold
Symbol
V
VDDMH
V
VDDML
V
VREGM
V
POR
t
RMP
t
POR
t
RST
Conditions
Early Warning
Reset
Early Warning
Reset
Early Warning
Rising Voltage on V
DD
Falling Voltage on V
DD
V
DD
Ramp Time
Reset Delay from POR
Reset Delay from non-POR source
Time to V
DD
> 1.8 V
Relative to V
DD
>
V
POR
Time between release
of reset source and
code execution
Min
2.10
1.95
1.81
1.70
4.2
—
0.8
10
3
—
Typ
2.20
2.05
1.85
1.74
4.4
1.4
1
—
—
10
Max
2.30
2.1
1.88
1.77
4.6
—
1.3
3000
100
—
Units
V
V
V
V
V
V
V
µs
ms
µs
RESET Low Time to Generate Reset
Missing Clock Detector Response
Time (final rising edge to reset)
Missing Clock Detector Trigger
Frequency
V
DD
Supply Monitor Turn-On Time
t
RSTL
t
MCD
F
MCD
t
MON
F
AHB
> 1 MHz
50
—
—
—
—
0.4
7.5
2
—
1
13
—
ns
ms
kHz
µs
Preliminary Rev. 0.8
15
SILABS [ SILICON LABORATORIES ]
