STK11C48
Internally,
RECALL
is a two-step procedure. First,
the
SRAM
data is cleared, and second, the nonvola-
tile information is transferred into the
SRAM
cells.
After the t
RECALL
cycle time the
SRAM
will once again
be ready for
READ
and
WRITE
operations. The
RECALL
operation in no way alters the data in the
Nonvolatile Element cells. The nonvolatile data can
be recalled an unlimited number of times.
HARDWARE PROTECT
The STK11C48 offers hardware protection against
inadvertent
STORE
operation during low-voltage
conditions. When V
CC
< V
SWITCH
, all software
STORE
operations are inhibited.
LOW AVERAGE ACTIVE POWER
The STK11C48 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between I
CC
and
READ
cycle
time. Worst-case current consumption is shown for
both
CMOS
and
TTL
input levels (commercial tem-
perature range, V
CC
= 5.5V, 100% duty cycle on
chip enable). Figure 3 shows the same relationship
for
WRITE
cycles. If the chip enable duty cycle is
less than 100%, only standby current is drawn
when the chip is disabled. The overall average cur-
rent drawn by the STK11C48 depends on the fol-
lowing items: 1)
CMOS
vs.
TTL
input levels; 2) the
duty cycle of chip enable; 3) the overall cycle rate
for accesses; 4) the ratio of
READ
s to
WRITE
s; 5)
the operating temperature; 6) the V
cc
level; and 7) I/
O loading.
100
POWER-UP
RECALL
During power up, or after any low-power condition
(V
CC
< V
RESET
), an internal
RECALL
request will be
latched. When V
CC
once again exceeds the sense
voltage of V
SWITCH
, a
RECALL
cycle will automatically
be initiated and will take t
RESTORE
to complete.
If the STK11C48 is in a
WRITE
state at the end of
power-up
RECALL
, the
SRAM
data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
V
CC
or between E and system V
CC
.
100
Average Active Current (mA)
80
Average Active Current (mA)
80
60
60
TTL
CMOS
20
40
TTL
20
CMOS
0
50
100
150
Cycle Time (ns)
200
40
0
50
100
150
Cycle Time (ns)
200
Figure 2: I
CC
(max) Reads
Figure 3: I
CC
(max) Writes
March 2006
8Document Control # ML0003 rev 0.2
SIMTEK [ SIMTEK CORPORATION ]
