Preliminary
SRAM WRITE CYCLES #1, #2, and #3
SYMBOLS
NO.
#1
15
16
17
18
19
20
21
22
23
24
25
t
AVAV
t
WLWH
t
ELWH
t
BLWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZ e, g
t
WHQX
#2
t
AVAV
t
WLEH
t
ELEH
t
BLEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
#3
t
AVAV
t
WLBH
t
ELBH
t
BLBH
t
DVBH
t
BHDX
t
AVBH
t
AVBL
t
BHAX
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Alt.
t
WC
t
WP
t
CW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Byte Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
3
PARAMETER
MIN
15
10
15
15
5
0
10
0
0
7
3
MAX
MIN
25
20
20
20
10
0
20
0
0
STK14EC16-15
STK14EC16
STK14EC16-25
MAX
STK14EC16-45
UNITS
MIN
45
30
30
30
15
0
30
0
0
10
3
15
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note g: If W is low when E goes low, the outputs remain in the high-impedance state.
Note h: E or W must be
≥
V
IH
during address transitions.
SRAM WRITE CYCLE #1: W Controlled
g,h
t
AVAV
(15)
Address
Address Valid
t
ELWH
(17)
t
WHAX
(23)
E
t
BLWH
(18)
LB, UB
W
t
AVWL
(22)
Data Input
t
WLQZ
(24)
Data Output
Previous Data
t
AVWH
(21)
t
WLWH
(16)
t
DVWH
(19)
t
WHDX
(20)
Input Data Valid
t
WHQX
(25)
High Impedance
SRAM WRITE CYCLE #2: E Controlled
g,h
t
AVAV
(15)
Address
t
AVWL
(22)
E
t
BLEH
(18)
LB , UB
t
WLEH
(16)
W
Data Input
t
DVEH
(19)
t
EHDX
(20)
Address Valid
t
ELEH
(17)
t
EHAX
(23)
Input Data Valid
High Impedance
Data Output
Document Control #ML0061 Rev 1.1
Jan, 2008
7
Simtek Confidential
SIMTEK [ SIMTEK CORPORATION ]
