STK15C88
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
MIN
MAX
MIN
MAX
(V
CC
= 5.0V
±
10%)
STK15C88-25
STK15C88-45
UNITS
12
13
14
15
16
17
18
19
20
21
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZ
h, i
t
WHQX
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
25
20
20
10
0
20
0
0
10
5
45
30
30
15
0
30
0
0
15
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note i:
Note j:
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be
≥
V
IH
during address transitions.
SRAM WRITE CYCLE #1: W Controlled
j
12
t
AVAV
ADDRESS
14
t
ELWH
E
17
t
AVWH
13
t
WLWH
15
t
DVWH
DATA IN
20
t
WLQZ
PREVIOUS DATA
DATA VALID
19
t
WHAX
18
t
AVWL
W
16
t
WHDX
DATA OUT
HIGH IMPEDANCE
21
t
WHQX
SRAM WRITE CYCLE #2:
E Controlled
j
12
t
AVAV
ADDRESS
18
t
AVEL
E
14
t
ELEH
19
t
EHAX
17
t
AVEH
W
13
t
WLEH
15
t
DVEH
16
t
EHDX
DATA VALID
DATA IN
DATA OUT
Document Control #ML0016 Rev 2.0
Jan, 2008
5
SIMTEK [ SIMTEK CORPORATION ]
