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U631H64BDC25 参数 Datasheet PDF下载

U631H64BDC25图片预览
型号: U631H64BDC25
PDF下载: 下载PDF文件 查看货源
内容描述: SoftStore 8K ×8的nvSRAM [SoftStore 8K x 8 nvSRAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 13 页 / 132 K
品牌: SIMTEK [ SIMTEK CORPORATION ]
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U631H64
Symbol
No. Software Controlled STORE/RECALL
Cycle
l, n
25 STORE/RECALL Initiation Time
26 Chip Enable to Output Inactive
o
27 STORE Cycle Time
p
28 RECALL Cycle Time
q
29 Address Setup to Chip Enable
r
30 Chip Enable Pulse Width
r, s
31 Chip Disable to Address Change
r
Alt.
IEC
25
35
45
Unit
Min. Max. Min. Max. Min. Max.
t
AVAV
t
ELQZ
t
ELQXS
t
ELQXR
t
AVELN
t
ELEHN
t
EHAXN
t
cR
t
dis(E)SR
t
d(E)S
t
d(E)R
t
su(A)SR
t
w(E)SR
t
h(A)SR
25
600
10
20
0
20
0
35
600
10
20
0
25
0
45
600
10
20
0
35
0
ns
ns
ms
μs
ns
ns
ns
n:
o:
p:
q:
r:
s:
The software sequence is clocked with E controlled READs.
Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
Note that STORE cycles (but not RECALL) are aborted by V
CC
< V
SWITCH
(STORE inhibit).
An automatic RECALL also takes place at power up, starting when V
CC
exceeds V
SWITCH
and takes t
RESTORE
. V
CC
must not drop below
V
SWITCH
once it has been exceeded for the RECALL to function properly.
Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
If the Chip Enable Pulse Width is less than t
a(E)
(see Read Cycle) but greater than or equal t
w(E)SR
, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
Software Controlled STORE/RECALL Cycle
r, s, t, u
(E = HIGH after STORE initiation)
t
cR
(25)
t
cR
(25)
ADDRESS 6
t
w(E)SR
(31)
t
h(A)SR
(30)
(31)
Ai
E
t
su(A)SR
(29)
ADDRESS 1
t
w(E)SR
(30)
DQi
Output
t
h(A)SR
t
su(A)SR
(29)
t
dis(E)
(5)
t
d(E)S
(27)
t
d(E)R
(28)
VALID
t
dis(E)SR
(26)
High Impedance
VALID
Software Controlled STORE/RECALL Cycle
r, s, t, u
(E = LOW after STORE initiation)
t
cR
(25)
Ai
E
t
su(A)SR
(29)
ADDRESS 1
t
w(E)SR
(30)
(31)
t
h(A)SR
(29)
ADDRESS 6
t
h(A)SR
(31)
DQi
Output
t
su(A)SR
t
d(E)S
(27)
t
d(E)R
(28)
High Impedance
VALID
VALID
t
dis(E)SR
(26)
W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U631H64 performs a STORE
or RECALL.
u: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
t:
STK Control #ML0045
8
Rev 1.0
March 31, 2006