U637256
Write Cycle #1: W-controlledj
tcW
(12)
Ai
Address Valid
tsu(E)
th(A
(21)
)
(17)
(16)
E
tsu(A-WH)
W
tw(W)
(13)
tsu(A)
(15)
th(D)
tsu(D)
(20)
(19)
Input Data Valid
ten(W)
DQi
Input
t
(23)
dis(W) (22)
Previous Data
DQi
High Impedance
Output
Write Cycle #2: E-controlledj
tcW
Address Valid
(12)
Ai
E
t
su(A)(15)
th(A)
(21)
tw(E)
(18)
tsu(W)
(14)
t
W
th(D)
Input Data Valid
High Impedance
su(D) (19)
(20)
DQi
Input
DQi
Output
undefined
L- to H-level
H- to L-level
i: If W is low and when E goes low, the outputs remain in the high impedance state.
j: E or W must be VIH during address transition.
Rev 1.1
August 15, 2006
STK Control #ML0054
6
SIMTEK [ SIMTEK CORPORATION ]
