U637256
Nonvolatile Memory Operations
Mode Selection
A13 - A0
(hex)
Note
s
E
W
Mode
I/O
Power
H
L
L
L
X
H
L
X
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
Standby
Active
Active
Active
m
H
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
k, l
k, l
k, l
k, l
k, l
k, l
Nonvolatile STORE
L
H
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k, l
Nonvolatile RECALL
k: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL
cycle tables and diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.
l: While there are 15 addresses on the U637256, only the lower 14 are used to control software modes.
Activation of nonvolatile cycles does not depend on the state of G.
m: I/O state assumes that G ≤±VIL.
Symbol
PowerStore
No.
Conditions
Min. Max. Unit
Power Up RECALL
Alt.
IEC
24 Power Up RECALL Durationn
25 STORE Cycle Durationf, e
tRESTORE
tPDSTORE
650
10
μs
ms
Time allowed to Complete SRAM
26
tDELAY
1
μs
Cyclef
Low Voltage Trigger Level
VSWITCH
4.0
4.5
V
n: tRESTORE starts from the time VCC rises above VSWITCH
.
August 15, 2006
STK Control #ML0054
7
Rev 1.1
SIMTEK [ SIMTEK CORPORATION ]
