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EMC2103-2-AP 参数 Datasheet PDF下载

EMC2103-2-AP图片预览
型号: EMC2103-2-AP
PDF下载: 下载PDF文件 查看货源
内容描述: 基于RPM的风扇控制器硬件过热关机 [RPM-Based Fan Controller with HW Thermal Shutdown]
分类和应用: 风扇控制器
文件页数/大小: 84 页 / 1193 K
品牌: SMSC [ SMSC CORPORATION ]
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RPM-Based Fan Controller with HW Thermal Shutdown
Datasheet
Table 6.26 Limit Registers (continued)
ADDR
39h **
3Ah **
3Ch
R/W
R/W
R/W
R/W
REGISTER
External Diode
2 Low Limit **
External Diode
3 Low Limit **
Internal Diode
Low Limit
B7
Sign
Sign
Sign
B6
64
64
64
B5
32
32
32
B4
16
16
16
B3
8
8
8
B2
4
4
4
B1
2
2
2
B0
1
1
1
DEFAULT
00h
(0°C)
00h
(0°C)
00h
(0°C)
The EMC2103 contains high limits for all temperature channels. If any measurement meets or exceeds
the high limit then the appropriate status bit is set and the ALERT pin is asserted (if enabled).
Additionally, the EMC2103 contains low limits for all temperature channels. If the temperature channel
drops below the low limit, then the appropriate status bit is set and the ALERT pin is asserted (if
enabled).
All Limit Registers are Software Locked.
6.20
Fan Setting Registers
Table 6.27 Fan Driver Setting Register
ADDR
40h
R/W
R/W
REGISTER
Fan Setting
B7
128
B6
64
B5
32
B4
16
B3
8
B2
4
B1
2
B0
1
DEFAULT
00h
The Fan Setting Register always displays the current setting of the Fan Driver. Reading from the
register will report the current fan speed setting of the fan driver regardless of the operating mode.
Therefore it is possible that reading from this register will not report data that was previously written
into this register.
While the RPM based Fan Speed Control Algorithm or the Look Up Table are active (or both), then
the register is read only. Writing to the register will have no affect and the data will not be stored.
If both the RPM based Fan Control Algorithm and the Look Up Table are disabled, then the register
will be set with the previous value that was used. The register is read / write and writing to this register
will affect the fan speed.
The contents of the register represent the weighting of each bit in determining the final duty cycle. The
output drive for a PWM output is given by
VALUE
-
Drive
=
--------------------
⎞ ×
100%
255
[1]
6.21
PWM Divide Register
Table 6.28 PWM Divide Register
ADDR
41h
R/W
R/W
REGISTER
PWM Divide
B7
128
B6
64
B5
32
B4
16
B3
8
B2
4
B1
2
B0
1
DEFAULT
01h
Revision 0.85 (01-29-08)
54
SMSC EMC2103
DATASHEET