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LAN8710AI-EZK-TR 参数 Datasheet PDF下载

LAN8710AI-EZK-TR图片预览
型号: LAN8710AI-EZK-TR
PDF下载: 下载PDF文件 查看货源
内容描述: MII / RMII 10/100以太网收发器, HP Auto-MDIX的和flexPWR技术在小尺寸 [MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR Technology in a Small Footprint]
分类和应用: 网络接口电信集成电路电信电路以太网局域网(LAN)标准以太网:16GBASE-T
文件页数/大小: 79 页 / 1095 K
品牌: SMSC [ SMSC CORPORATION ]
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MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR
®
Technology in a Small Footprint
Datasheet
Table 5.29 Register 17 - Mode Control/Status (continued)
ADDRESS
17.6
NAME
ALTINT
DESCRIPTION
Alternate Interrupt Mode.
0 = Primary interrupt system enabled (Default).
1 = Alternate interrupt system enabled.
See
Write as 0, ignore on read.
1 = PHY disregards PHY address in SMI access
write.
0 = normal operation;
1 = force 100TX- link active;
Note:
17.1
ENERGYON
This bit should be set only during lab testing
RO
X
MODE
RW
DEFAULT
0
17.5:4
17.3
17.2
Reserved
PHYADBP
Force
Good Link Status
RW
RW
RW
00
0
0
ENERGYON – indicates whether energy is detected
on the line (see
it goes to “0” if no valid
energy is detected within 256ms. Reset to “1” by
hardware reset, unaffected by SW reset.
Write as 0. Ignore on read.
17.0
Reserved
RW
0
Table 5.30 Register 18 - Special Modes
ADDRESS
18.15
18.14
NAME
Reserved
MIIMODE
DESCRIPTION
Write as 0, ignore on read.
MII Mode:
set the mode of the digital interface, as
described in
0 – MII interface.
1 – RMII interface
Write as 0, ignore on read.
Transceiver Mode of operation. Refer to
for
more details.
PHY Address.
The PHY Address is used for the SMI address and for
the initialization of the Cipher (Scrambler) key. Refer
to
for more details.
Table 5.31 Register 26 - Symbol Error Counter
ADDRESS
26.15:0
NAME
Sym_Err_Cnt
DESCRIPTION
100Base-TX receiver-based error register that
increments when an invalid code symbol is received
including IDLE symbols. The counter is incremented
only once per packet, even when the received packet
contains more than one symbol error. The 16-bit
register counts up to 65,536 (2
16
) and rolls over to 0
if incremented beyond that value. This register is
cleared on reset, but is not cleared by reading the
register. It does not increment in 10Base-T mode.
MODE
RO
DEFAULT
0
MODE
RW
RW,
NASR
DEFAULT
0
X
18.13:8
18.7:5
Reserved
MODE
RW,
NASR
RW,
NASR
RW,
NASR
000000
XXX
18.4:0
PHYAD
PHYAD
Revision 1.0 (04-15-09)
44
SMSC LAN8710/LAN8710i
DATASHEET