CXA1315M/P
SW, SAD Pins
No.
8
8
9
10
11
Item
Low level input
voItage
High level input
voltage
Low level input
current
High level input
current
Low level input
voltage
Symbol Test
circuit
V
IL
V
IH
I
IL
I
IH
V
OL
4
4
4
4
5
Test conditions
Input voltage where ST0 to ST3 become "0"
Min. Typ. Max. Unit
—
—
—
0
0
0.2
1.5
—
+10
+10
0.4
V
V
µA
µA
V
Input voltage where ST0 to ST3 become "1" 3.0
lnput current when 0.4V is applied
lnput current when 4.5V is applied
SW 0 to 3 = 1,
Output voltage when 1mA flows in
–10
–10
0
I
2
C Bus Block Items (SDA, SCL)
No.
13 High level input voltage
14 Low level input voltage
15 High level input current
16 Low level input current
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Item
Symbol
V
IH
V
IL
I
IH
I
IL
V
OL
I
OL
C
I
f
SCL
t
BUF
t
HD; STA
t
LOW
t
HIGH
t
SU; STA
t
HD; DAT
t
SU; DAT
t
R
t
F
t
SU; STO
Min. Typ. Max.
3.0 — 5.0
— 1.5
0
— 10
—
— 10
—
— 0.4
0
— —
3
— 10
—
— 100
0
4.7 — —
4.0 — —
4.7 — —
4.0 — —
4.7 — —
— —
5
250 — —
—
1
—
— 300
—
4.7 — —
Unit
V
V
µA
µA
V
mA
pF
kHz
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
Low level output voltage, at 3mA flow to SDA (Pin 14)
Maximum flowing current
lnput capacitance
Maximum clock frequency
Data change minimum waiting time
Data transfer start minimum waiting time
Low level clock pulse width
High level clock pulse width
Minimum start preparation waiting time
Minimum data hold time
Minimum data preparation time
Rise time
Fall time
Minimum stop preparation waiting time
I
2
C bus load conditions: Pull-up resistance 4kΩ (Connected to +5V)
Load capacitance 200pF (Connected to GND)
I
2
C Bus Control Signal
SDA
t
BUF
t
R
t
F
t
HD; STA
SCL
t
LOW
P
S t
HD; STA
t
HD; DAT
t
HIGH
t
SU; DAT
Sr
t
SU; STA
t
SU; STO
P
–4–
SONY [ SONY CORPORATION ]
