CXA1315M/P
Definition of I
2
C Bus Register
<SIave address>
MSB
0
1
0
0
SAD2 SAD1 SAD0
LSB
R/W
R/W 0: SLAVE RECEIVER
1: SLAVE TRANSMITTER
SAD0 to 2:11 to13 pin
0: "Low"
1: "High"
<Register table>
•
•
•
•
•
With the lC reset all registers are reset to "0"
∗:
Not defined
x: Don't care
Sub address is auto incremented
lt can be used as a 6-bit D/A converter by setting the lower two bits of DAC0 to 4 registers to "0", but take
care that the max. voltage of DA output will lower about 100mV compared with the use of 8 bits.
Control Register
Sub address
x x x x x 0 0 0
x x x x x 0 0 1
x x x x x 0 1 0
x x x x x 0 1 1
x x x x x 1 0 0
x x x x x 1 0 1
Bit 7
REF
Bit 6
∗
Bit 5
∗
Bit 4
∗
Bit 3
SW3
DAC0 (8)
DAC1 (8)
DAC2 (8)
DAC3 (8)
DAC4 (8)
Bit 2
SW2
Bit 1
SW1
Bit 0
SW0
Status Register
Bit 7
PONRES
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
ST3
Bit 2
ST2
Bit 1
ST1
Bit 0
ST0
–6–
SONY [ SONY CORPORATION ]
