CXA1315M/P
•
I
2
C data write (Write from I
2
C controller to IC)
At "L" during write
MSB
SDA
Hi-Z
MSB
LSB
Hi-Z
SCL
S
MSB
1
2
3
4
5
6
7
8
9
1
8
9
Address
LSB
Hi-Z
Hi-Z
ACK
Sub Address
ACK
1
8
9
1
8
9
DATA (n)
Hi-Z
ACK
DATA (n + 1)
Hi-Z
ACK
DATA (n + 2)
∗
The number of data that can be
8
9
1
8
9
P
transferred at a time is confined to
units of 8-bit that can be set as required.
Sub Address is incremented automatically.
DATA
ACK
DATA
ACK
•
I
2
C data read (Read from IC to I
2
C controller)
At "H" during read
SDA
Hi-Z
SCL
S
1
6
Address
7
8
9
ACK
1
7
DATA
8
9
ACK
P
•
Read timing
MSB
IC output SDA
LSB
SCL
9
1
2
3
4
5
6
7
8
9
Read timing
ACK
DATA
ACK
∗
Data read is performed with SCL rise.
–8–