CXP853P40A
(2) Serial transfer
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Condition
Input mode
Min.
1000
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK cycle time
SCK
tKCY
1
Output mode
8000/fc'
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK
t
KH
KL
SCK
SI
High and Low level widths
t
400
1
4000/fc' – 50
SI input setup time
(referenced to SCK ↑)
t
t
t
SIK
100
200
200
100
SI input hold time
(referenced to SCK ↑)
SI
KSI
200
100
SCK ↓ → SO delay time
SO
KSO
Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
1
The value of fc' varies as shown below depending on the specification of oscillation clock option.
4MHz version ... fc' = fc
8MHz version ... fc' = fc/2
tKCY
tKL
tKH
0.8VDD
0.2VDD
SCK
tSIK
tKSI
0.8VDD
0.2VDD
Input data
SI
tKSO
0.8VDD
SO
Output data
0.2VDD
Fig. 4. Serial transfer timing
– 15 –
SONY [ SONY CORPORATION ]
