ICX055BL
Block Diagram and Pin Configuration
V
OUT
V
GG
V
SS
GND
Vφ
2
Vφ
1
Vφ
3
Vφ
4
1
Note
Horizontal register
Note)
9
10
11
12
13
14
15
16
: Photo sensor
(Top View)
8
7
6
5
4
3
2
Vertical register
V
L
GND
SUB
Pin Description
Pin No.
1
2
3
4
5
6
7
8
Symbol
Vφ
4
Vφ
3
Vφ
2
Vφ
1
GND
V
GG
V
SS
V
OUT
Description
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Output amplifier gate bias
Output amplifier source
Signal output
Pin No.
9
10
11
12
13
14
15
16
Symbol
V
DD
GND
SUB
V
L
RG
NC
Hφ
1
Hφ
2
Horizontal register transfer clock
Horizontal register transfer clock
Description
Output amplifier drain supply
GND
Substrate (Overflow drain)
Protective transistor bias
Reset gate clock
Absolute Maximum Ratings
Item
Substrate voltage SUB – GND
Supply voltage
V
DD
, V
OUT
, V
SS
– GND
V
DD
, V
OUT
, V
SS
– SUB
Vφ
1
, Vφ
2
, Vφ
3
, Vφ
4
– GND
Vφ
1
, Vφ
2
, Vφ
3
, Vφ
4
– SUB
Ratings
–0.3 to +55
–0.3 to +18
–55 to +10
–15 to +20
to +10
to +15
to +17
–17 to +17
–10 to +15
–55 to +10
–65 to +0.3
–0.3 to +30
–0.3 to +24
–0.3 to +20
–30 to +80
–10 to +60
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
∗
1
Remarks
Vertical clock input voltage
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
Hφ
1
, Hφ
2
– Vφ
4
Hφ
1
, Hφ
2
, RG, V
GG
– GND
Hφ
1
, Hφ
2
, RG, V
GG
– SUB
V
L
– SUB
Vφ
1
, Vφ
2
, Vφ
3
, Vφ
4
, V
DD
, V
OUT
– V
L
RG – V
L
V
GG
, Vss, Hφ
1
, Hφ
2
– V
L
Storage temperature
Operating temperature
*
1
+27V (Max.) when clock width<10µs, clock duty factor<0.1%.
–2–
V
DD
Hφ
1
Hφ
2
RG
NC
SONY [ SONY CORPORATION ]
