ICX055BL
Clock Voltage Conditions
Item
Readout clock voltage
Symbol
V
VT
V
VH1
, V
VH2
V
VH3
, V
VH4
V
VL1
, V
VL2
,
V
VL3
, V
VL4
Vφ
V
Vertical transfer clock
voltage
|V
VH1
– V
VH2
|
V
VH3
– V
VH
V
VH4
– V
VH
V
VHH
V
VHL
V
VLH
V
VLL
Horizontal transfer
clock voltage
Reset gate clock
voltage
Vφ
H
V
HL
Vφ
RG
V
RGLH
– V
RGLL
22.5
23.5
4.75
–0.05
4.5
5.0
0
5.0
–0.25
–0.25
Min.
14.55
–0.05
–0.2
–9.0
7.8
Typ.
15.0
0
0
–8.5
8.5
Max.
15.45
0.05
0.05
–8.0
9.05
0.1
0.1
0.1
0.5
0.5
0.5
0.5
5.25
0.05
5.5
0.8
24.5
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Waveform
diagram
1
2
2
2
2
2
2
2
2
2
2
2
3
3
4
4
5
∗
1
Low-level coupling
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
V
VL
= (V
VL3
+ V
VL4
) /2
Vφ
V
= V
VH
n – V
VL
n (n = 1 to 4)
V
VH
= (V
VH1
+ V
VH2
) /2
Remarks
Substrate clock voltage Vφ
SUB
∗
1
The reset gate clock voltage need not be adjusted when reset gate clock is driven when the specifications
are as given below. In this case, the reset gate clock voltage setting indicated on the back of the image
sensor has not significance.
Waveform
diagram
4
4
Item
Reset gate clock
voltage
Symbol
V
RGL
Vφ
RG
Min.
–0.2
8.5
Typ.
0
9.0
Max.
0.2
9.5
Unit
V
V
Remarks
–4–
SONY [ SONY CORPORATION ]
