S29GL064N90TFI030 参数 Datasheet PDF下载

D at a

S hee t

Figure 15.9

Toggle Bit Timings (During Embedded Algorithms)

t

AHT

Addresses

t

AHT

t

ASO

CE#

t

OEH

WE#

t

OEPH

OE#

t

DH

DQ6 / DQ2

Valid Data

Valid

Status

t

AS

t

CEPH

t

CE

Valid

Status

Valid

Status

Valid Data

(first read)

RY/BY#

(second read)

(stops toggling)

Note

VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array

data read cycle.

Figure 15.10

DQ2 vs. DQ6

Enter

Embedded

Erasing

WE#

Erase

Suspend

Erase

Enter Erase

Suspend Program

Erase

Suspend

Program

Erase

Resume

Erase Suspend

Read

Erase

Erase

Complete

Erase Suspend

Read

DQ6

DQ2

Note

DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.

70

S29GL-N MirrorBit

®

Flash Family

S29GL-N_01_09 November 16, 2007