D at a
S hee t
Figure 15.11
Alternate CE# Controlled Write (Erase/Program) Operation Timings
PBA for program
2AA for erase
SA for program buffer to flash
SA for sector erase
555 for chip erase
Data# Polling
PA
Addresses
t
WC
t
WH
WE#
t
GHEL
OE#
t
CP
CE#
t
WS
t
CPH
t
DS
t
DH
Data
t
RH
PBD for program
55 for erase
29 for program buffer to flash
30 for sector erase
10 for chip erase
t
AS
t
AH
t
WHWH1 or 2
t
BUSY
DQ7#
D
OUT
RESET#
RY/BY#
Notes
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. D
OUT
is the data written to the device.
4. Illustration shows device in word mode.
72
S29GL-N MirrorBit
®
Flash Family
S29GL-N_01_09 November 16, 2007