CY28317-2
Pin Definitions
Pin Name
CPU0, CPU1
CPUT, CPUC
PCI2:6
PCI1/FS3
Pin No.
48, 47
44, 43
13, 14, 15,
16, 17
11
Pin Type
O
O
O
I/O
Pin Description
CPU Clock Output 0 through 1:
CPU clocks for processor and chipset.
Differential CPU Clock Output:
Differential CPU clocks for processor.
PCI Clock Outputs 2 through 6:
3.3V 33-MHz PCI clock outputs. Frequency
is set by FS0:4 inputs or through serial data interface.
Fixed PCI Clock Output/Frequency Select 3:
3.3V PCI clock outputs. As an
output, the frequency is set by FS0:4 inputs or through serial data interface. This
pin also serves as a power-on strap option to determine device operating
frequency, as described in
Table 6.
Fixed PCI Clock Output/Frequency Select 4:
3.3V Free-running PCI clock
outputs. This pin also serves as a power-on strap option to determine device
operating frequency as described in
Table 6.
Reset# Output:
Open drain system reset output.
PCI0_F/FS4
10
I/O
RST#
41
O
(open-drai
n)
I/O
48MHz/FS0
27
48 MHz Output/Frequency Select 0:
3.3V 48-MHz non-spread spectrum
output. This pin also serves as a power-on strap option to determine device
operating frequency as described in
Table 6.
24_48MHz Output/Frequency Select 1:
3.3V 24 or 48 MHz non-spread
spectrum output. This pin also serves as a power-on strap option to determine
device operating frequency as described in
Table 6.
Reference Clock Output 1/Frequency Select 2:
3.3V 14.318 MHz output
clock. This pin also serves as a power-on strap option to determine device
operating frequency as described in
Table 6.
Reference Clock Output 0:
3.3V 14.318-MHz output clock.
SDRAM Buffer Input Pin:
Reference input for SDRAM buffer.
SDRAM Outputs:
These thirteen dedicated outputs provide copies of the signal
provided at the SDRAMIN input.
Clock pin for SMBus circuitry.
Data pin for SMBus circuitry.
Crystal Connection or External Reference Frequency Input:
This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection or
as an external reference frequency input.
Crystal Connection:
An output connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
Power Down Control:
LVTTL-compatible input that places the device in
power-down mode when held LOW.
CPU Output Control:
3.3V LVTTL compatible input that stops CPU0, CPU1,
CPUT, and CPUC when held LOW.
PCI Output Control:
3.3V LVTTL compatible input that stop PCI1:6 when held
LOW.
Current Reference Input:
Current reference for differential CPU output.
CPUT and CPUC Output Control:
Control the current multiplier for differential
CPU output. Set this pin LOW for 1.0V output swing and set this pin HIGH for
0.7V output swing.
VTT_PWRGD#:
3.3V LVTTL compatible input that controls the FS0:4 to be
latched and enables all outputs. CY28316 will sample the FS0:4 inputs and
enable all clock outputs after all the VDD become valid and VTT_PWRGD# is
held LOW.
24_48MHz/
FS1
REF1/FS2
26
I/O
2
I/O
REF0
SDRAMIN
SDRAM0:6
SCLK
SDATA
X1
3
18
37, 36, 34,
33, 31, 30, 39
25
24
7
O
I
O
I
I/O
I
X2
PD#
CPU_STOP#
PCI_STOP#
IREF
MULT_SEL
8
21
19
20
40
22
O
I
I
I
I
I
VTT_PWRGD#
4
I
Rev 1.0, November 25, 2006
Page 2 of 20
SPECTRALINEAR [ SPECTRALINEAR INC ]
