CY28317-2
Byte 6: Watchdog Timer Register
(continued)
Bit
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
WD_TIMER4
WD_TIMER3
WD_TIMER2
WD_TIMER1
WD_TIMER0
WD_PRE_SC
ALER
Default
1
1
1
1
1
0
Pin Description
These bits store the time-out value of the Watchdog Timer. The scale of the
timer is determined by the prescaler.
The timer can support a value of 150 ms to 4.8 sec when the prescaler is set
to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec
to 80 sec.
When the Watchdog Timer reaches “0,” it will set the WD_TO_STATUS bit and
generate Reset if RST_EN_WD is enabled.
0 = 150 ms
1 = 2.5 sec
Byte 7: Control Register 7
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
–
25
26
–
–
–
–
–
Name
Reserved
24_48MHz_DRV
48MHz_DRV
Reserved
Reserved
Reserved
Reserved
Reserved
Default
0
1
1
0
0
0
0
0
Reserved
0 = Norm, 1 = High Drive
0 = Norm, 1 = High Drive
Reserved
Reserved
Reserved
Reserved
Reserved
Pin Description
Byte 8: Vendor ID and Revision ID Register (Read Only)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Revision_ID3
Revision_ID2
Revision_ID1
Revision_ID0
Vendor_ID3
Vendor_ID2
Vendor _ID1
Vendor _ID0
Default
0
0
0
0
1
0
0
0
Revision ID bit[3]
Revision ID bit[2]
Revision ID bit[1]
Revision ID bit[0]
Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read-only.
Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read-only.
Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read-only.
Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read-only.
Pin Description
Byte 9: System RESET and Watchdog Timer Register
Bit
Bit 7
Name
SDRAM_DRV
Default
0
Pin Description
SDRAM clock output drive strength
0 = Normal
1 = High Drive
PCI clock output drive strength
0 = Normal
1 = High Drive
Reserved
This bit will enable the generation of a Reset pulse when a Watchdog Timer
time-out occurs.
0 = Disabled
1 = Enabled
Bit 6
PCI_DRV
0
Bit 5
Bit 4
Reserved
RST_EN_WD
0
0
Rev 1.0, November 25, 2006
Page 8 of 20
SPECTRALINEAR [ SPECTRALINEAR INC ]
