CY28317-2
Byte 9: System RESET and Watchdog Timer Register
(continued)
Bit
Bit 3
Name
RST_EN_FC
Default
0
Pin Description
This bit will enable the generation of a Reset pulse after a frequency change
occurs.
0 = Disabled
1 = Enabled
Watchdog Timer Time-out Status bit
0 = No time-out occurs (Read); Ignore (Write)
1 = Time-out occurred (Read); Clear WD_TO_STATUS (Write)
0 = Stop and reload Watchdog Timer. Unlock CY28317-2 from recovery
frequency mode.
1 = Enable Watchdog Timer. It will start counting down after a frequency change
occurs.
Note:
CY28317-2 will generate a system reset, reload a recovery frequency,
and lock itself into a recovery frequency mode after a Watchdog Timer time-out
occurs. Under recovery frequency mode, CY28317-2 will not respond to any
attempt to change output frequency via the SMBus control bytes. System
software can unlock CY28317-2 from its recovery frequency mode by clearing
the WD_EN bit.
CPU0:1 clock output drive strength
0 = Normal
1 = High Drive
Bit 2
WD_TO_STATUS
0
Bit 1
WD_EN
0
Bit 0
CPU0:1_DRV
0
Byte 10: Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Name
CPU0:1_Skew2
CPU0:1_Skew1
CPU0:1_Skew0
Default
0
0
0
CPU 0:1 output skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
Reserved
Reserved
Reserved
CPUT and CPUC output skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
Description
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
CPUT&C_Skew1
CPUT&C_Skew0
0
0
0
0
0
Rev 1.0, November 25, 2006
Page 9 of 20
SPECTRALINEAR [ SPECTRALINEAR INC ]
