CY28326
Table 2. Mode Ratio Setting
Power-up Condition
Mode
0
0
1
1
Table 3. Ratio mapping Table
Power-up Frequency value
CPU
100
133
200
166
AGP
66.6
66.6
66.6
66.6
FS1
0
0
1
1
FS[1:0]
FS0
0
1
0
1
Ratio pin mapping
Pin 20
0
0
1
1
Pin 19
0
1
0
1
RatioSel
x
x
0
1
Pin 19
PCI_STP#
PCI_STP#
Ratio0
PCI5
Pin I/O Setting
Pin 20
CPU_STP#
CPU_STP#
Ratio1
PCI6
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. The interface can also be
accessed during power down operation.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
Table 4. Command Code Definition
Bit
7
0 = Block read or block write operation
1 = Byte read or byte write operation
block write and block read operation from any external I
2
C
controller. For block write/read operation, the bytes must be
accessed in sequential order from lowest to highest byte (most
significant bit first) with the ability to stop after any complete
byte has been transferred. For byte write and byte read opera-
tions, the system controller can access individual indexed
bytes. The offset of the indexed byte is encoded in the
command code, as described in
Table 4.
The block write and
block read protocol is outlined in
Table 5
while
Table 6
outlines
the corresponding byte write and byte read protocol.The slave
receiver address is 11010010 (D2h).
Description
(6:5) Device selection bits. Set = 00
(4:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 5. Block Read and Block Write protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 Bits
Acknowledge from slave
Byte Count – 8 bits
(Skip this step if I
2
C_EN bit set)
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 Bits
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Block Read Protocol
Description
Rev 1.0, November 20, 2006
Page 4 of 22
SPECTRALINEAR [ SPECTRALINEAR INC ]
