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CY28341OC-3 参数 Datasheet PDF下载

CY28341OC-3图片预览
型号: CY28341OC-3
PDF下载: 下载PDF文件 查看货源
内容描述: 通用时钟芯片为VIA ™ P4M / KT / KM400A DDR系统 [Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems]
分类和应用: 晶体外围集成电路光电二极管双倍数据速率时钟
文件页数/大小: 19 页 / 264 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28341-3  
Table 4. Byte Read and Byte Write Protocol (continued)  
Byte Write Protocol  
Byte Read Protocol  
Description  
Bit  
Description  
Bit  
28  
29  
Stop  
Read = 1  
29  
Acknowledge from slave  
Data byte from slave – 8 bits  
Acknowledge from master  
Stop  
30:37  
38  
39  
Serial Control Registers  
Byte 0: Frequency Select Register  
Bit  
7
@Pup  
0
Pin#  
Name  
Reserved  
FS2  
Description  
Reserved  
6
H/W Setting  
H/W Setting  
H/W Setting  
0
21  
10  
1
For Selecting Frequencies in Frequency Selection Table on page 1  
For Selecting Frequencies in Frequency Selection Table on page 1  
For Selecting Frequencies in Frequency Selection Table on page 1  
5
FS1  
4
FS0  
3
FS_Override If this bit is programmed to “1”, it enables WRITE to bits (6:4,1) for  
selecting the frequency via software (SMBus)  
If this bit is programmed to a “0” it enable only READ of bits (6:4,1),  
which reflect the hardware setting of FS(0:3).  
2
1
0
0
11  
20  
7
Reserved  
FS3  
Reserved, set = 0  
H/W Setting  
H/W Setting  
For Selecting frequencies in Frequency Selection Table on page 1  
SELP4_K7  
Only for reading the hardware setting of the CPU interface mode,  
status of SELP4_K7# strapping.  
Byte 1: CPU Clocks Register  
Bit @Pup Pin#  
Name  
Description  
7
6
5
4
3
0
1
1
1
1
MODE  
SSCG  
SST1  
SST0  
0 = Down Spread. 1 = Center Spread. See Table 9 on page 8  
1 = Enable (default). 0 = Disable  
Select spread bandwidth. See Table 9 on page 8  
Select spread bandwidth. See Table 9 on page 8  
48,49 CPUCS_T, CPUCS_C  
1 = output enabled (running). 0 = output disabled asynchronously in a low  
state.  
2
1
1
0
53,52 CPUT/CPUOD_T  
CPUC/CPUOD_C  
1 = output enabled (running). 0 = output disable.  
53,52 CPUT/C  
In K7 mode, this bit is ignored.In P4 mode, 0 = when PD# asserted LOW,  
CPUT stops in a high state, CPUC stops in a low state. In P4 mode, 1 = when  
PD# asserted LOW, CPUT and CPUC stop in High-Z.  
0
1
11 MULT0  
Only for reading the hardware setting of the Pin11 MULT0 value.  
Byte 2: PCI Clock Register  
Bit  
7
@Pup  
Pin#  
Name  
PCI_DRV  
Description  
0
1
1
1
1
PCI clock output drive strength 0 = Low strength, 1 = High strength  
1 = output enabled (running). 0 = output disabled asynchronously in a low state.  
1 = output enabled (running). 0 = output disabled asynchronously in a low state.  
1 = output enabled (running). 0 = output disabled asynchronously in a low state.  
1 = output enabled (running). 0 = output disabled asynchronously in a low state.  
6
10  
18  
17  
15  
PCI_F  
PCI6  
PCI5  
PCI4  
5
4
3
Rev 1.0,November 21, 2006  
Page 5 of 19