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CY28341OC-3 参数 Datasheet PDF下载

CY28341OC-3图片预览
型号: CY28341OC-3
PDF下载: 下载PDF文件 查看货源
内容描述: 通用时钟芯片为VIA ™ P4M / KT / KM400A DDR系统 [Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems]
分类和应用: 晶体外围集成电路光电二极管双倍数据速率时钟
文件页数/大小: 19 页 / 264 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28341-3  
Swing Select Functions Through Hardware  
Board Target  
Trace/Term Z  
Reference R,  
IREF = VDD/(3*Rr)  
MULTSEL  
Output Current  
VOH@Z  
1
50 Ohm  
Rr = 475 1%,  
IREF = 2.32mA  
IOH = 6* Iref  
0.7V@50  
Meanwhile, the system BIOS is running its operation with the  
new frequency. If this device receives a new SMBus command  
to clear the bits originally programmed in the Watchdog timer  
bits (reprogram to 0000) before the Watchdog times out, then  
this device will keep operating in its normal condition with the  
new selected frequency.  
Watchdog Self-Recovery Sequence  
This feature is designed to allow the system designer to  
change frequency while the system is running and reboot the  
operation of the system in case of a hang-up due to the  
frequency change.  
When the system sends an SMBus command requesting a  
frequency change through the Dial-a-Frequency Control  
Registers, it must have previously sent a command to the  
Watchdog timer to select which time-out stamp the Watchdog  
must perform, otherwise the System Self-Recovery feature will  
not be applicable. Consequently, this device will change  
frequency and then the Watchdog timer starts timing.  
The Watchdog timer will also be triggered if you program the  
software frequency select bits (FSEL) to a new frequency  
selection. If the Watchdog times out before the new SMBus  
reprograms the Watchdog timer bits to (0000), then this device  
send a low system reset pulse, on SRESET# and changes  
Watchdog time-out bit to “1”.  
W
AT C H D O G T IM ER  
PR O G R AM M IN G  
R ESET W AT C H D O G T IM ER  
Set W D T imer Bits =  
C lear W D Alarm bit  
0
0
=
IN IT IAL IZ EW AT C H D O G T IM ER  
Set F req uency R evert Bit  
Set W D T imer Bits  
C H AN G E F R EQ B Y  
SET SO F T W AR EF SEL  
Set SW F req _Sel bits  
Set F S override bit  
C H AN G E F R EQ B Y SET D IAL -A-  
F R EQ U EN C Y  
C H AN G E F R EQ B Y  
SET D IAL -A-R AT IO  
Load  
M and N R eg isters  
1
Select  
a different divider ratio  
Set Pro_F req _EN  
=
C O U N T D O W N W D T IM ER  
Send 3ms R eset Pulse  
NO  
W
D T im er = 0  
C L EAR W D T IM ER  
Set W D Alarm  
=
1
F req u en cy R ev ert B it =  
Set F req uency to  
F S_H W_Latched  
0
F req u en cy R ev ert B it =  
Set F req uency to  
F S_SW Setting  
1
SR ESET # = 0 fo r 3 m sec  
R eset & R ev ert  
F req u en cy b ack  
Figure 1. Watchdog Self Recovery Sequence Flowchart  
Rev 1.0,November 21, 2006  
Page 9 of 19