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CY28341OC-3 参数 Datasheet PDF下载

CY28341OC-3图片预览
型号: CY28341OC-3
PDF下载: 下载PDF文件 查看货源
内容描述: 通用时钟芯片为VIA ™ P4M / KT / KM400A DDR系统 [Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems]
分类和应用: 晶体外围集成电路光电二极管双倍数据速率时钟
文件页数/大小: 19 页 / 264 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28341-3  
Byte 2: PCI Clock Register (continued)  
2
1
0
1
1
1
14  
12  
11  
PCI3  
PCI2  
PCI1  
1 = output enabled (running). 0 = output disabled asynchronously in a low state.  
1 = output enabled (running). 0 = output disabled asynchronously in a low state.  
1 = output enabled (running). 0 = output disabled asynchronously in a low state.  
Byte 3: AGP/Peripheral Clocks Register  
Bit  
@Pup  
Pin#  
Name  
Description  
24_48M  
0 = pin21 output is 24MHz. Writing a '1' into this register asynchronously  
changes the frequency at pin21 to 48 MHz.  
7
0
21  
6
5
4
3
2
1
0
1
1
0
0
1
1
1
20  
21  
48MHz  
1 = output enabled (running). 0 = output disabled asynchronously in a low  
1 = output enabled (running). 0 = output disabled asynchronously in a low  
24_48M  
6,7,8  
6,7,8  
8
DASAG1  
DASAG0  
AGP2  
ProgrammingthesebitsallowshiftingskewoftheAGP(0:2)signalsrelative  
to their default value. See Table 5.  
1 = output enabled (running). 0 = output disabled asynchronously in a low  
1 = output enabled (running). 0 = output disabled asynchronously in a low  
1 = output enabled (running). 0 = output disabled asynchronously in a low  
7
AGP1  
6
AGP0  
Table 5. Dial-a-Skew¥ AGP(0:2)  
DASAG (1:0)  
AGP(0:2) Skew Shift  
00  
01  
10  
11  
Default  
–280 ps  
+280 ps  
+480 ps  
Byte 4: Peripheral Clocks Register  
Bit  
7
@Pup  
Pin#  
20  
Name  
Description  
1 = Low strength, 0 = High strength  
1
1
0
0
1
1
1
1
48M  
6
21  
24_48M  
1 = Low strength, 0 = High strength  
5
6,7,8  
6,7,8  
1
DARAG1  
DARAG0  
REF0  
Programming these bits allow modifying the frequency ratio of the  
AGP(2:0), PCI(6:1, F) clocks relative to the CPU clocks. See Table 6.  
4
3
1 = output enabled (running). 0 = output disabled asynchronously in a low  
1 = output enabled (running). 0 = output disabled asynchronously in a low  
1 = Low strength, 0 = High strength  
2
56  
REF1  
1
1
REF0  
0
56  
REF1  
1 = Low strength, 0 = High strength (K7 Mode only)  
Table 6. Dial-A-Ratio¥ AGP(0:2)  
DARAG (1:0)  
CU/AGP Ratio  
00  
01  
10  
11  
Frequency Selection Default  
2/1  
2.5/1  
3/1  
Byte 5: SDR/DDR Clock Register  
Bit  
@Pup  
Pin#  
Name  
BUF_IN  
Description  
7
0
45  
DDR Mode, BUF_IN threshold setting. 0 = 1.15V, 1 = 1.05V  
threshold  
voltage  
6
5
1
1
46  
FBOUT  
1 = output enabled (running). 0 = output disabled asynchronously in a low state.  
1 = output enabled (running). 0 = output disabled asynchronously in a low state.  
29,30 DDRT/C5  
Rev 1.0,November 21, 2006  
Page 6 of 19