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CY28346ZCT 参数 Datasheet PDF下载

CY28346ZCT图片预览
型号: CY28346ZCT
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟合成器,差分CPU输出 [Clock Synthesizer with Differential CPU Outputs]
分类和应用: 晶体外围集成电路光电二极管时钟
文件页数/大小: 19 页 / 221 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28346
Byte 6: Silicon Signature Register
[4]
(all bits are Read-only)
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
1
0
0
1
1
Vendor Code = 0011
Pin#
Revision = 0001
Description
Byte 7: Reserved Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Pin#
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Description
Byte 8: Dial-a-Frequency Control Register N
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
N6, MSB
N5
N4
N3
N2
N3
N0, LSB
Name
Reserved. Set = 0.
These bits are for programming the PLL’s internal N register. This access allows the user to
modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks
(clocks that are generated from the same PLL, such as PCI) remain at their existing ratios
relative to the CPU clock.
Description
Byte 9: Dial-a-Frequency Control Register R
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
R5, MSB
R4
R3
R2
R1
R0
DAF_ENB
R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded
from DAF (SMBus) registers.
Name
Reserved. Set = 0.
These bits are for programming the PLL’s internal R register. This access allows the user to
modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks
(clocks that are generated from the same PLL, such as PCI) remain at their existing ratios
relative to the CPU clock.
Description
Note:
4. When writing to this register, the device will acknowledge the Write operation, but the data itself will be ignored.
Rev 1.0, November 24, 2006
Page 5 of 19