CY28347
Maximum Ratings
[3]
Input Voltage Relative to V
SS
:...............................V
SS
– 0.3V
Input Voltage Relative to V
DDQ
or AV
DD
: ............. V
DD
+ 0.3V
Storage Temperature: ................................ –65 C to + 150 C
Operating Temperature:.................................... 0 C to +70 C
Maximum ESD............................................................. 2000V
Maximum Power Supply: ................................................ 5.5V
This device contains circuitry to protect the inputs against
damage due to HIGH static voltages or electric field. However,
precautions should be take to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For
proper operation, V
IN
and V
OUT
should be constrained to the
range.
V
SS
< (V
IN
or V
OUT
) < V
DD
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Parameters
(V
DD
= V
DDPCI
= V
DDAGP
= V
DDR
= V
DD48M
= V
DDC
= 3.3V ± 5%, V
DDI
= V
DD
= 2.5 ± 5%, T
A
= 0 °C to +70 °C)
Parameter
VIL1
VIH1
VIL2
VIH2
Vol
Iol
Ioz
Idd3.3V
Idd2.5V
Ipd
Ipup
Ipdwn
Cin
Cout
Lpin
Cxtal
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage for Sreset#
Pull-down Current for Sreset#
Three-state Leakage Current
Dynamic Supply Current
Dynamic Supply Current
Power-down Supply current
Internal Pull-up Device Current
Internal Pull-down Device Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
Crystal Pin Capacitance
Measured from the X
IN
or X
OUT
to V
SS
27
36
CPU frequency set at 133.3
[4]
CPU frequency set at 133.3
PD# = 0
Input @ V
SS
Input @ V
DD
MHz
[4]
156
177
3.8
IOL
VOL = 0.4V
Applicable to SDATA and SCLK
2.2
0.4
24
35
10
180
200
4.0
–25
10
5
6
7
45
Conditions
Applicable to PD#, F S(0:4)
2.0
1.0
Min.
Typ.
Max.
1.0
Unit
Vdc
Vdc
Vdc
Vdc
V
mA
A
mA
mA
mA
A
A
pF
pF
pF
pF
AC Parameters
66 MHz
Parameter
Crystal
TDC
TPeriod
VHIGH
VLOW
Tr / Tf
TCCJ
Txs
Description
Xin Duty Cycle
Xin Period
Xin HIGH Voltage
Xin LOW Voltage
Xin Rise and Fall Times
Xin Cycle to Cycle Jitter
Crystal Start-up Time
Min.
45
69.84
0.7V
DD
0
Max.
55
71.0
V
DD
0.3V
DD
10.0
500
30
100 MHz
Min.
45
69.84
0.7V
DD
0
Max.
55
71.0
V
DD
0.3V
DD
10.0
500
30
133 MHz
Min.
45
69.84
0.7V
DD
0
Max.
55
71.0
V
DD
0.3V
DD
10
500
30
200 MHz
Min.
45
69.84
0.7V
DD
0
Max. Unit
55
71.0
V
DD
0.3V
DD
10
500
30
Notes
% 5,6,7,8
ns 5,6,7,8
V 7,9
V
ns 7
ps 10,11,12,13
ms 9
Notes:
3.
Multiple Supplies:
The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. All outputs loaded as per maximum capacitative load table in P4 and DDR mode. See
Table 12.
5. All outputs loaded as per loading specified in the loading table. See
Table 12.
6. This measurement is applicable with Spread ON or spread OFF.
7. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.
8. The typical value of VX is expected to be 0.5*VDDD (or 0.5*VDDC for CPUCS signals) and will track the variations in the DC level of the same.
9. Measured between 0.2Vdd and 0.7Vdd.
10. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for 2.5V signals, and between
20% and 80% for differential signals.
11. Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals.
12. When Xin is driven from and external clock source (3.3V parameters apply).
13. When Crystal meets minimum 40 ohm device series resistance specification.
Rev 1.0, November 20, 2006
Page 9 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
