CY28347
Table 6. Byte Read and Byte Write Protocol
(continued)
10
11:18
Acknowledge from slave
Command Code - 8 bits “1xxxxxxx” stands for byte
operation bit[6:0] of the command code represents
the offset of the byte to be accessed
Acknowledge from slave
Data Byte from Master – 8 Bits
Acknowledge from slave
Stop
10
11:18
Acknowledge from slave
Command Code - 8 bits “1xxxxxxx” stands for byte
operation bit[6:0] of the command code represents
the offset of the byte to be accessed
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read
Acknowledge from slave
Data byte from slave - 8 bits
Not Acknowledge
Stop
19
20:27
28
29
19
20
21:27
28
29
30:37
38
39
Byte 0: Frequency Select Register
Bit
7
6
5
4
3
@Pup
0
H/W Setting
H/W Setting
H/W Setting
0
21
10
1
FS2
FS1
FS0
Pin#
Name
Reserved.
For Selecting Frequencies see
Table 1.
For Selecting Frequencies see
Table 1.
For Selecting Frequencies see
Table 1.
If this bit is programmed to “1,” it enables WRITES to bits (6:4,1) for
selecting the frequency via software (SMBus)
If this bit is programmed to a “0” it enables only READS of bits
(6:4,1), which reflect the hardware setting of FS(0:3).
11
20
7
Reserved
FS3
SELP4_K7#
Reserved
For Selecting frequencies in
Table 1.
Only for reading the hardware setting of the CPU interface mode,
status of SELP4_K7# strapping.
Description
2
1
0
H/W Setting
H/W Setting
H/W Setting
Byte 1: CPU Clocks Register
Bit
7
6
5
4
3
2
1
@Pup
0
1
1
1
1
1
0
48,49
53,52
53,52
Pin#
Name
SSMODE
SSCG
SST1
SST0
CPUCS_T/C_ EN#
CPUOD_T/C_EN#
CPUT/C_PD_CNTRL
Description
0 = Down Spread. 1 = Center Spread. See
Table 10.
1 = Enable (default). 0 = Disable
Select spread bandwidth. See
Table 10.
Select spread bandwidth. See
Table 10.
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
1 = output enabled (running). 0 = output disable asynchronously
in a LOW state.
In K7 mode, this bit is ignored. In P4 mode, when PD# asserted
LOW, 0 = drive CPUT to 2xIref and CPUC LOW and
1 = three-state CPUT and CPUC.
Only For reading the hardware setting of the Pin11 MULT0 value.
0
1
11
MULT0
Byte 2: PCI Clock Register
Bit
7
6
5
@Pup
0
1
1
10
Pin#
Name
PCI_DRV
PCI_F
Description
PCI clock output drive strength 0 = Normal, 1 = increase the drive
strength 20%.
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
Reserved, set = 1.
Rev 1.0, November 20, 2006
Page 5 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
