CY28347
Byte 2: PCI Clock Register
(continued)
Bit
4
3
2
1
0
@Pup
1
1
1
1
1
Pin#
17
15
14
12
11
Name
PCI5
PCI4
PCI3
PCI2
PCI1
Description
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
Byte 3: AGP/Peripheral Clocks Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
1
1
0
0
1
1
1
7
6
AGP1
AGP0
Pin#
21
20
21
6,7,8
6,7,8
Name
24_48M
48MHz
24_48M
DASAG1
DASAG0
Description
“0” = pin 21 output is 24 MHz. Writing a “1” into this register
asynchronously changes the frequency at pin 21 to 48 MHz.
1 = output enabled (running). 0 = output disabled asynchro-
nously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchro-
nously in a LOW state.
Programming these bits allow shifting skew of the AGP(0:2)
signals relative to their default value. See
Table 7.
Reserved, set = 1.
1 = output enabled (running). 0 = output disabled asynchro-
nously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchro-
nously in a LOW state.
Byte 4: Peripheral Clocks Register
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
0
0
1
1
1
1
Pin#
20
21
6,7,8
6,7,8
1
56
1
56
Name
48M
24_48M
DARAG1
DARAG0
REF0
REF1
REF0
REF1
Description
1 = strength x 1. 0= strength x 2
1 = strength x 1. 0= strength x 2
1 = strength x 1. 0= strength x 2
1 = strength x 1. 0= strength x 2
Programming these bits allow modifying the frequency ratio of
the AGP(2:0), PCI(6:1, F) clocks relative to the CPU clocks. See
Table 8.
1 = output enabled (running). 0 = output disabled asynchro-
nously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchro-
nously in a LOW state. (K7 Mode only.)
1 = strength x 1. 0 = strength x 2
1 = strength x 1. 0 = strength x 2 (K7 Mode only)
Table 7. Dial-a-Skew™ AGP(0:2)
DASAG (1:0)
00
01
10
11
AGP(0:2) Skew Shift
Default
–280 ps
+280 ps
+480 ps
Rev 1.0, November 20, 2006
Page 6 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
