CY28400-2
SRC_STP Deassertion
All differential outputs that were stopped will resume normal
operation in a glitch-free manner. The maximum latency from
the deassertion to active outputs is between 2–6 DIFT/C clock
periods (2 clocks are shown) with all DIFT/C outputs resuming
simultaneously. If the control register tri-state bit is
programmed to ‘1’ (tri-state), then all stopped DIFT outputs will
be driven high within 15 ns of SRC_STP deassertion to a
voltage greater than 200 mV.
1 ms
SRC_STP
PWRDWN
DIFT(Free Running
DIFC(Free Running
DIFT (Stoppable)
DIFC (Stoppable)
Figure 6. SRC_STP = Driven, PWRDWN = Driven, OE_INV = 0
1 ms
SRC_STP
PWRDWN
DIFT(Free Running
DIFC(Free Running
DIFT (Stoppable)
DIFC (Stoppable)
Figure 7. SRC_STP = Tri-state, PWRDWN = Driven, OE_INV = 0
1 ms
SRC_STP
PWRDWN
DIFT(Free Running
DIFC(Free Running
DIFT (Stoppable)
DIFC (Stoppable)
Figure 8. SRC_STP = Tri-state, PWRDWN = Tri-state, OE_INV = 0
Rev 1.0, November 21, 2006
Page 8 of 15
SPECTRALINEAR [ SPECTRALINEAR INC ]
