CY28400-2
Byte 0: Control Register 0
(continued)
Bit
5
4
3
2
1
0
@pup
0
0
0
1
1
1
Reserved
Reserved
Reserved
HIGH_BW#
PLL/BYPASS#
SRC_DIV2#
Name
Reserved
Reserved
Reserved
HIGH_BW#
0 = High Bandwidth, 1 = Low bandwidth
PLL/BYPASS#
0 = Fanout buffer, 1 = PLL mode
SRC_DIV2# configures output frequency at half the input frequency
0 = Divided by 2 mode (output = input/2),1 = Normal (output = input)
Description
Byte 1: Control Register 1
Bit
7
6
@pup
1
1
Reserved
OE_6
Name
Reserved
DIF[T/C]6 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
DIF[T/C]5 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
Reserved
Reserved
DIF[T/C]2 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
DIF[T/C]1 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
Reserved
Description
5
1
OE_5
4
3
2
1
1
1
Reserved
Reserved
OE_2
1
1
OE_1
0
1
Reserved
Byte 2: Control Register 2
Bit
7
6
@pup
0
0
Reserved
SRC_STP_DIF[T/C]6
Name
Reserved
Allow Control DIF[T/C]6 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Allow Control DIF[T/C]5 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Reserved
Reserved
Allow Control DIF[T/C]2 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Allow Control DIF[T/C]1 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Reserved
Description
5
0
SRC_STP_DIF[T/C]5
4
3
2
0
0
0
Reserved
Reserved
SRC_STP_DIF[T/C]2
1
0
SRC_STP_DIF[T/C]1
0
0
Reserved
Rev 1.0, November 21, 2006
Page 4 of 15
SPECTRALINEAR [ SPECTRALINEAR INC ]
