CY28400-2
Byte 3: Control Register 3
Bit
7
6
5
4
3
2
1
0
@pup
0
0
0
0
0
0
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Byte 4: Vendor ID Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
1
0
0
0
Name
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
Byte 5: Control Register 5
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
OE_INV Clarification
The OE_INV pin is an input strap sampled at power-on. The
functionality of this input is to set the active level polarities for
OE_1, OE_6, PWRDWN, and SRC_STP input pins. ‘Active
HIGH’ indicates the functionality of the input is asserted when
the input voltage level at the pin is high and deasserted when
the voltage level at the input is low. ‘Active LOW’ indicates that
the functionality of the input is asserted when the voltage level
at the input is low and deasserted when the voltage level at the
input pin is high. See V
IH
and V
IL
in the DC Electrical Specifi-
cations for input voltage high and low ranges.
OE_INV
0
1
PWRDWN
Active LOW
Active HIGH
SRC
Active LOW
Active HIGH
OE_1, OE_6
Active HIGH
Active LOW
PWRDWN Clarification
The PWRDWN pin is an asynchronous input used to shut off
all clocks cleanly and instruct the device to evoke power
savings mode. It may be active HIGH or active LOW
depending on the strapped value of the OE_INV input. The
PWRDWN pin should be asserted prior to shutting off the input
clock or power to ensure all clocks shut down in a glitch-free
manner. This signal is synchronized internal to the device prior
to powering down the clock buffer. PWRDWN is an
asynchronous input for powering up the system. When the
PWRDWN pin is asserted, all clocks will be held high or
tri-stated (depending on the state of the control register drive
mode and OE bits) prior to turning off the VCO. All clocks will
start and stop without any abnormal behavior and meet all AC
and DC parameters. This means no glitches, frequency
shifting or amplitude abnormalities among others.
Rev 1.0, November 21, 2006
Page 5 of 15
SPECTRALINEAR [ SPECTRALINEAR INC ]
