CY28401
Byte 2: Control Register 2
(continued)
Bit
3
@pup
0
Name
Description
Allow Control DIF_3 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
Allow Control DIF_2 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
Allow Control DIF_1 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
Allow Control DIF_0 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
2
0
1
0
0
0
Byte 3: Control Register 3
Bit
7
6
5
4
3
2
1
0
@pup
0
0
0
0
0
0
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Byte 4: Vendor ID Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
1
0
0
0
Name
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
Byte 5: Control Register 5
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Rev 1.0, November 21, 2006
Page 5 of 13
SPECTRALINEAR [ SPECTRALINEAR INC ]
