CY28419
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low-ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
The following diagram shows a typical crystal configuration
using the two trim capacitors. An important clarification for the
following discussion is that the trim capacitors are in series
with the crystal not parallel. It’s a common misconception that
load capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is
not true.
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capac-
itance on each side of the crystal must be twice the specified
load capacitance(CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capac-
itors(Ce1,Ce2) should be calculated to provide equal capaci-
tative loading on both sides.
Use the following formulas to calculate the trim capacitor
values fro Ce1 and Ce2.
Load Capacitance (each side)
Ce
= 2 * CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
CLe
=
1
(
Ce1 + Cs1 + Ci1
+
1
1
Ce2 + Cs2 + Ci2
)
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
..................................... using standard value trim capacitors
Ce..................................................... External trim capacitors
Figure 1. Crystal Capacitive Clarification
Cs ........................................... Stray capacitance (trace, etc.)
Ci ...........................................................Internal capacitance
................................................ (lead frame, bond wires, etc.)
PD# (Power-down) Clarification
The PD# pin is used to shut off all clocks and PLLs without
having to remove power from the device. All clocks are shut
down in a synchronous manner so has not to cause glitches
while transitioning to the power-down state.
PD#–Assertion
When PD# is sampled low by two consecutive rising edges of
the CPUC clock then all clock outputs (except CPU) clocks
must be held low on their next high to low transition. CPU
clocks must be held with CPUT clock pin driven high with a
value of 2x Iref and CPUC undriven as the default condition.
There exists an I2C bit that allows for the CPUT/C outputs to
be three-stated during power-down. Due to the state of internal
logic, stopping and holding the REF clock outputs in the LOW
state may require more than one clock cycle to complete.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Clock Chip
(CY28419)
Ci1
Ci2
Pin
3 to 6p
Cs1
X1
X2
Cs2
Trace
2.8pF
XTAL
Ce1
Ce2
Trim
33pF
Figure 2. Crystal Loading Example
Rev 1.0, November 22, 2006
Page 8 of 15
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