CY28443-3
Byte 8: Control Register 8
(continued)
Bit
1
0
@Pup
1
1
PCIF0
Name
RESERVED
RESERVED, Set = 1
33-MHz Output Drive Strength
0 = Low, 1 = High
Description
Byte 9: Control Register 9
Bit
7
6
5
4
@Pup
0
0
0
0
S3
S2
S1
S0
Name
Description
27_96_100_SSC Spread Spectrum Selection table:
S[3:0] SS%
‘0000’ = –0.5%(Default value)
‘0001’ = –1.0%
‘0010’ = –1.5%
‘0011’ = –2.0%
‘0100’ = ±0.25%
‘0101’ = ±0.5%
‘0110’ = ±0.75%
‘0111’ = ±1.0%
‘1000’ = –0.35%
‘1001’ = –0.68%
‘1010’ = –1.09%
‘1011’ = –1.425%
‘1100’ = ±0.17%
‘1101’ = ±0.34%
‘1110’ = ±0.545%
‘1111’ = ±0.712%
RESERVED, Set = 1
27-MHz Spread Output Enable
0 = Disable (Hi-Z), 1 = Enable
27M_SS/LCD100M Spread spectrum enable.
0 = Disable, 1 = Enable.
33-MHz Output Drive Strength
0 = Low, 1 = High
3
2
1
0
1
1
1
0
RESERVED
27M Spread
27M_SS/LCD100M
Spread Enable
PCIF1
Byte 10: Control Register 10
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
0
0
0
0
Name
SRC[T/C]11
SRC[T/C]9
RESERVED
SRC[T/C]8
SRC[T/C]9
SRC[T/C]11
RESERVED
SRC[T/C]8
SRC[T/C]11 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]9 Output Enable
0 = Disable (Hi-Z), 1 = Enable
RESERVED, Set = 1
SRC[T/C]8 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Allow control of SRC[T/C]9 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]11 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
RESERVED, Set = 0
Allow control of SRC[T/C]8 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Description
Rev 1.0, November 20, 2006
Page 8 of 23
SPECTRALINEAR [ SPECTRALINEAR INC ]
