SL23EP08SC-1H 参数 Datasheet PDF下载

SL23EP08

Figure 1. CLKIN Input to CLKA and CLKB Delay

S2

0

0

1

1

S1

0

1

0

1

Clock A1-A4

Tri-state

Driven

Driven

Driven

Clock B1-B4

Tri-state

Tri-state

Driven

Driven

Output Source

PLL

PLL

Reference(CLKIN)

PLL

PLL Shutdown

and Bypass

Yes

No

Yes

No

Table 2. Select Input Decoding

Device

SL23EP08-1 and 1H

SL23EP08-2 and -2H

SL23EP08-2 and -2H

SL23EP08-3

SL23EP08-3

[1]

[1]

[1]

[1]

Feedback From

Bank-A or Bank-B

Bank-A

Bank-B

Bank-A

Bank-B

Bank-A or Bank-B

Bank-A or Bank-B

Bank-A Frequency

Reference

Reference

2x Reference

2xReference

4xReference

2x Reference

Reference/2

Bank-B Frequency

Reference

Reference/2

Reference

Reference

[2]

2xReference

2x Reference

Reference/2

SL23EP08-4

SL23EP08-5H

Table 3. Available SL23EP08 Configurations

Notes:

1. Outputs are inverted on SL23EP08-2, -2H and -3 in PLL bypass mode when S2=1 and S1=0. Use SL23EP08-1 if

non-inverting outputs are required.

2. Output phase is random (0° or 180° with respect to input clock). Use SL23EP08-2 if phase integrity is required.

Rev 1.4, May 28, 2007

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