1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
A11
A9
A8
A13
A14
NC
WE#
Vcc
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard Pinout
Top View
Die up
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3
304 MSW F01.1
1
2
3
4
5
F
IGURE
1: P
IN
A
SSIGNMENTS FOR
32-
PIN
TSOP P
ACKAGES
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
23
22
21
20
19
18
17
Vcc
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
DQ1
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
4
A12
A15
A16
NC
WE#
Vcc
NC
6
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
3
2
1
32 31 30
29
28
27
26
7
8
9
304 MSW F02.1
32-Pin PDIP
Top View
24
32-Lead PLCC
Top View
25
24
23
22
21
14 15 16
17 18 19
20
DQ2
Vss
DQ4
DQ6
DQ3
DQ5
10
11
12
13
14
15
16
F
IGURE
2: P
IN
A
SSIGNMENTS FOR
32-
PIN
P
LASTIC
DIP
S AND
32-
LEAD
PLCC
S
T
ABLE
2: P
IN
D
ESCRIPTION
Symbol
Pin Name
A
16
-A
7
Row Address Inputs
A
6
-A
0
DQ
7
-DQ
0
Column Address
Inputs
Data Input/output
Functions
To provide memory addresses. Row addresses define a page for a
write cycle.
Column Addresses are toggled to load page data.
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs are in
tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the write operations
To provide 5-volt supply (± 10%) for the 29EE010, 3-volt supply (3.0-3.6V)
for the 29LE010 and 2.7-volt supply (2.7-3.6V) for the 29VE010
Unconnected pins.
304 PGM T2.0
CE#
OE#
WE#
Vcc
Vss
NC
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
© 1998 Silicon Storage Technology, Inc.
5
304-04 12/97
SST [ SILICON STORAGE TECHNOLOGY, INC ]
